Multi-Port Memory Architecture For Storing Multi-Dimensional Arrays II

ABSTRACT

An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

FIELD OF THE INVENTION

The present invention relates to digital systems design in general, and,more particularly, to the architecture of a multi-port memory.

BACKGROUND OF THE INVENTION

FIG. 1 depicts a block diagram of a multi-processor and a multi-portmemory. In general, the fact that the multi-processor comprises aplurality of execution units causes it to actually or virtually accessmore than one word within the memory at a time. There are threewell-known memory architectures in the prior art for doing so.

In accordance with the first architecture, a full N-port design isemployed that allows any N memory locations to be accessed from any portwithout blocking. The full N-port design is the fastest of themulti-port architectures, but is also the largest.

In accordance with the second architecture, a single-port memory withcontention resolution is employed that functions as a single-server,multi-queue system. The single-port memory with contention resolution isthe slowest of the multi-port architectures, but is also the smallest.

In accordance with the third architecture, a plurality of independentmemory banks with contention resolution are employed. So long as eachprocessor seeks data in a different memory bank, there is no contention.In contrast, when two processors seek data in the same memory bank,there is contention and one of them has to wait. An advantage of thethird architecture is that its speed and size are a function of thenumber of memory banks used, and, therefore, its space-time parameterscan be tailored for the application. For example, when the thirdarchitecture has a large number of memory banks, its speed and sizeapproach that of the full N-port design, but when the third architecturehas only 2 memory banks, it's speed and size approach that of thesingle-port memory.

FIG. 2 depicts a graph of the space-time parameters for three multi-portarchitectures in the prior art.

Although the three principal architectures provide a variety ofspace-time parameters, there are special-purpose applications that needa multi-port architecture with better space-time parameters than areexhibited by architectures in the prior art.

SUMMARY OF THE INVENTION

The present invention is an N-port memory architecture that is fasterthan a traditional N-bank memory bank architecture and smaller than afull N-port design. This is accomplished by recognizing that there arespecial-purpose applications where the traditional N-bank memory bankarchitecture can be enhanced to provide almost the same speed as thefull N-port design. One of these applications has to do with the storageof multi-dimensional arrays.

The illustrative embodiment is an memory bank architecture that has beenenhanced in two ways. First, the architecture has been modified to storemulti-dimensional arrays so that: (1) N contiguous elements in a row canbe accessed without blocking, (2) N contiguous elements in a column canbe accessed without blocking, (3) some N-element multi-dimensionalsub-arrays can be accessed without blocking, and (4) all N/2-elementmulti-dimensional sub-arrays can be accessed without blocking. This isadvantageous in system designs that handle multi-dimensional arrays,such as video decoding systems, etc.

Second, the architecture has been modified so that the above can happenand that any element can be read from, and written to, on any data port.This is particularly advantageous for loading and unloading data intothe vector registers of a single-instruction, multiple-data processor,such as that used for video decoding.

The illustrative embodiment comprises: (i) A address ports, wherein A isa positive integer greater than one; (ii) D data ports, wherein D is apositive integer greater than one; (iii) N independent memory banks,wherein N is a positive integer greater than one; (iv) an address switchfor routing addresses on said address ports to said memory banks,wherein said routing is based, at least in part, on said addresses; and(v) a data switch for routing data between said data ports and saidmemory banks, wherein said routing is based, at least in part, on (1)said addresses, and (2) which of said addresses is on which of saidaddress ports.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a block diagram of a multi-processor and a multi-portmemory.

FIG. 2 depicts a graph of the space-time complexity for three multi-portarchitectures in the prior art.

FIG. 3 depicts a block diagram of an N-port memory in accordance withthe illustrative embodiment of the present invention in which N=8.

FIG. 4 depicts a block diagram of the logical structure of memory 301,which is of a linear memory with P memory locations identified byaddresses 0 through P−1, wherein P is a positive integer greater than 1.

FIG. 5 depicts a block diagram of the salient components of memory 301,which comprises storage 501, N=8×N=8 data switch 502, and N=8×N=8address switch and decoder 503, interconnected as shown.

FIG. 6 depicts a block diagram of the salient components of storage 501,which comprises N=8 independent memory banks 501-1 through 501-8.

FIG. 7 a depicts a mapping of the elements in a multi-dimensional arrayto memory banks.

FIG. 7 b depicts how N contiguous elements of a the first column are allstored in different memory banks, and, therefore, can be read withoutcontention.

FIG. 7 c depicts how N contiguous elements in the third row are allstored in different memory banks, and, therefore, can be read withoutcontention.

FIG. 7 d depicts how a subarray of N/2 contiguous elements—elements(3,2), (4,2), (3,3), and (4,3)—are all stored in different memory banks,and, therefore, can be read without contention.

FIG. 7 e depicts how some, but not all, subarrays of N contiguouselements are stored in different memory banks, and, therefore, can beread without contention.

FIG. 8 depicts a mapping of multi-dimensional array elements to logicaladdresses.

FIG. 9 depicts a mapping of logical addresses to memory banks.

FIG. 10 depicts a block diagram of the salient components of addressswitch and decoder 502, which comprises N=8×N=8 address switch 1001 andaddress decoder 1002.

DETAILED DESCRIPTION

FIG. 3 depicts a block diagram of an N-port memory in accordance withthe illustrative embodiment of the present invention in which N=8. Itwill be clear to those skilled in the art, after reading thisspecification, how to make and use alternative embodiments of thepresent invention for any value in which N is a positive integer.

Memory 301 comprises N=8 data ports and N=8 address ports. A word can beread from or written to memory 301 on a data port independently ofwhether a word is read from or written to memory 301 on another port. Inother words, any combination of N=8 words can be read from and writteninto memory 301 in one cycle. For example, a word can be written intomemory 301 on data ports 1, 6, and 8, while words are read from memory301 on data ports 2, 3, 4, 5, and 7. In all cases, the data on port n,wherein nε{1, 2, . . . , N}, is associated with the address on addressport n.

FIG. 4 depicts a block diagram of the logical structure of memory 301,which is a linear memory with P memory locations identified by addresses0 through P−1, and wherein P is a positive integer greater than 1. Inaccordance with the illustrative embodiment, P=16,384=0x3FFF=2̂14, but itwill be clear to those skilled in the art how to make and usealternative embodiments of the present invention for any value of P. Soalthough memory 301 has multiple ports, the reading of an address on oneaddress port yields the same data as on another port because they bothrefer to the same logical memory location.

FIG. 5 depicts a block diagram of the salient components of memory 301,which comprises storage 501, N=8×N=8 data switch 502, and N=8×N=8address switch and decoder 503, interconnected as shown.

Storage 501 comprises P memory locations, N address ports, 510-1 through510-8, and N data ports, 513-1 through 513-8. In accordance with theillustrative embodiment, each logical memory location corresponds toonly one of the address ports 510-1 through 510-8 and one of the dataports 513-1 through 513-8.

The constraint that each logical memory location in memory 501corresponds to only one of the address ports 510-1 through 510-8 meansthat a logical address on one of address ports 511-1 through 511-8 mustbe routed to the correct one of address ports 510-1 through 510-8. Thisis the function performed by address switch and decoder 503. In otherwords, address switch and decoder 503 must:

-   -   i. decode each logical address on each of address ports 511-1        through 511-8,    -   ii. generate a physical memory address in storage 501 that        corresponds to that logical address, and    -   iii. route the physical address to the appropriate one of        address ports 510-1 through 510-8.        In accordance with the illustrative embodiment, address switch        and decoder 503 comprises an N×N non-blocking crossbar switch,        but it will be clear to those skilled in the art, after reading        this specification, how to make and use alternative embodiments        of the present invention in which another structure provides the        requisite functionality.

The shuffling of addresses between address ports 511-1 through 511-8 andaddress ports 510-1 through 510-8, without more, destroys the isomorphicrelationship in which the data on port 512-n is associated with theaddress on address port 511-n. To preserve this relationship, dataswitch 502 performs the inverse shuffle of address switch and decoder503. For example, if logical address 0x0000 is presented on address port511-3 during a read operation, the data in logical address 0x0000 shouldappear on data port 512-3. But within memory 301, address switch anddecoder 503 might route the corresponding physical address to addressport 510-1 which would cause the desired word to emerge on data port513-1. To ensure that the word emerges on data port 512-3, data switch513 routes the word from data port 513-1 to 512-3.

In accordance with the illustrative embodiment, data switch 502 is anN×N non-blocking crossbar switch, but it will be clear to those skilledin the art, after reading this specification, how to make and usealternative embodiments of the present invention in which anotherstructure provides the requisite functionality.

There is another advantage to the combination of address switch anddecoder 503 and data switch 502 and that is that it enables the word atany logical address to be read from, or written to, any of data ports512-1 through 512-8. This is particularly advantageous when, forexample, memory 301 is used to load and unload the vector registers in asingle-instruction, multiple-data processor.

FIG. 6 depicts a block diagram of the salient components of storage 501,which comprises N=8 independent memory banks 601-1 through 601-8. Eachmemory bank is a single-port memory that comprises P/N=2̂13=2048 words.Because storage 501 comprises independent memory banks only one wordfrom each memory bank can be read or written to in a single cycle.

Although the worst-case contention situation cannot be eliminated theaverage-case can be by distributing words that are often accessedtogether across different memory banks. There are special-purposeapplications where group of words are often accessed together and one ofthose applications involves the storage of multi-dimensional arrays,such as those commonly manipulated in video coding and coding (e.g.,H.264, MPEG, etc.). For example, in video decoding, the elements in arow, a column, and a contiguous block tend to be accessed far morefrequently together than random elements in the array.

In accordance with the illustrative embodiment, each element of a J×Ktwo-dimensional array, wherein J and K are both positive integersgreater than 1, is assigned to one of the memory banks so that threeconditions are satisfied:

-   -   i. the coordinates for N contiguous elements in a row of the        two-dimensional array decode into different memory banks; and    -   ii. the coordinates for N contiguous elements in a column of the        two-dimensional array decode into different memory banks; and    -   iii. the coordinates for the elements in an L by M        two-dimensional subarray of the two-dimensional array decode        into different memory banks, wherein L and M are both positive        integers, 1≦L≦J, 1≦M≦K, and 2≦L*M≦N/2.

It will be clear to those skilled in the art, after reading thisdisclosure, how to generate any of the many suitable mappings betweenarray coordinates and memory banks—and one illustrative mapping isdepicted in FIG. 7a.

FIG. 7 b depicts how N contiguous elements of a the first column are allstored in different memory banks, and, therefore, can be read withoutcontention. The reader can verify that the same is true for all columns.

FIG. 7 c depicts how N contiguous elements in the third row are allstored in different memory banks, and, therefore, can be read withoutcontention. The reader can verify that the same is true for all columns.

FIG. 7 d depicts how a subarray of N/2 contiguous elements—elements(3,2), (4,2), (3,3), and (4,3)—are all stored in different memory banks,and, therefore, can be read without contention. The reader can verifythat the same is true for all subarrays of N/2 contiguous elements.

FIG. 7 e depicts how some, but not all, subarrays of N contiguouselements are stored in different memory banks, and, therefore, can beread without contention. The reader can verify that the same is true forsome, but not all, subarrays of N contiguous elements.

One corollary of the above constraints is that, in accordance with thePigeon Hole Principal, at least two coordinates for any N+1 elementsdecode into the same memory bank.

In accordance with the illustrative embodiment, each element of a J×Ktwo-dimensional array is assigned a logical address in, for example,row-column order as depicted in FIG. 8. It will be clear to thoseskilled in the art how to assign the elements to logical addresses inaccordance with a different, but suitable, scheme.

In addition, address switch and decoder 503 comprises logic for decodingeach of the addresses into:

-   -   i. a memory bank, and    -   ii. a unique physical address into that memory bank        so that the following three conditions are satisfied:    -   i. addresses p+(c−1) decode into different memory banks for all        p and all c, wherein 0≦p+(c−1)<P, wherein p is a positive        integer and pε{0, . . . , P−1}, wherein c is a positive integer        and cε{1, . . . , C}, and wherein C is a positive integer and        C≦N; and    -   ii. addresses p+N(r−1) decode into different memory banks for        all p and all r, wherein 0≦p+N(r−1)<P, wherein r is a positive        integer and rε{1, . . . R}, and wherein R is a positive integer        and R≦N; and    -   iii. addresses p+(c−1)+N(r−1) decode into different memory banks        for all p, all c, and all r, wherein 0≦p+(c−1)+N(r−1)<P, and        wherein 1≦C*R≦N/2.

The result will be a mapping of logical addresses to memory banks, suchas that depicted in FIG. 9.

Here too, because there are only N memory banks, the Pigeon HolePrincipal holds—at least two addresses in every set of N+1 addressesdecode into the same memory bank.

FIG. 10 depicts a block diagram of the salient components of addressswitch and decoder 502, which comprises N=8×N=8 address switch 1001 andaddress decoder 1002.

Address switch 1001 is combinational logic that receives a P-bit logicaladdress on each of address ports 511-1 through 511-8 and that outputs a(log₂P-log₂N)-bit physical address on each of address ports 510-1through 510-8. Address switch 1001 shuffles the addresses under thecontrol of address decoder 1002 using a non-blocking cross-bar switch,but performs the logical address to physical memory address translationon its own so that each P-bit logical address assigned to a singlememory bank generates a unique (log₂P-log₂N)-bit physical address. Itwill be clear to those skilled in the art how to accomplish this.

It is to be understood that the above-described embodiments are merelyillustrative of the present invention and that many variations of theabove-described embodiments can be devised by those skilled in the artwithout departing from the scope of the invention. It is thereforeintended that such variations be included within the scope of thefollowing claims and their equivalents.

1. An apparatus comprising: (i) A address ports, wherein A is a positiveinteger greater than one; (ii) D data ports, wherein D is a positiveinteger greater than one; (iii) N independent memory banks, wherein N isa positive integer greater than one; (iv) an address switch for routingaddresses on said address ports to said memory banks, wherein saidrouting is based, at least in part, on said addresses; and (v) a dataswitch for routing data between said data ports and said memory banks,wherein said routing is based, at least in part, on (1) said addresses,and (2) which of said addresses is on which of said address ports. 2.The apparatus of claim 1 wherein said apparatus comprises P memorylocations identified by addresses 0 through P−1, wherein P is a positiveinteger greater than 1; and wherein said address switch is non-blockingfor all combinations of addresses p+(c−1) for all p and all c, wherein0≦p+(c−1)<P, wherein p is a positive integer and pε{0, . . . , P−1},wherein c is a positive integer and cε{1, . . . , C}, and wherein C is apositive integer and C≦N; wherein said address switch is blocking for atleast one combination of addresses p+(c−1) for all p and all c when C>N;wherein said address switch is non-blocking for all combinations ofaddresses p+N(r−1) for all p and all r, wherein 0≦p+N(r−1)<P, wherein ris a positive integer and rε{1, . . . , R}, and wherein R is a positiveinteger and R≦N; and wherein said address switch is blocking for atleast one combination of addresses p+N(r−1) for all p and all r whenR>N.
 3. The apparatus of claim 2 wherein said address switch isnon-blocking for addresses p+(c−1)+N(r−1) for all p, all c, and all r,wherein 0≦p+(c−1)+N(r−1)<P, and wherein 1≦C*R≦N.
 4. The apparatus ofclaim 1 wherein said apparatus comprises P memory locations identifiedby addresses 0 through P−1, wherein P is a positive integer greater than1; and wherein said address switch is non-blocking for all combinationsof addresses p+(c−1)+N(r−1) for all p, all c, and all r, wherein0≦p+(c−1)+N(r−1)<P, wherein p is a positive integer and pε{0, . . . ,P−1}, wherein c is a positive integer and cε{1, . . . , C}, wherein r isa positive integer and rε{1, . . . , R}, and wherein C and R arepositive integers and 1≦C*R≦N; and wherein said address switch isblocking for at least one combination of addresses p+(c−1)+N(r−1) forall p and all c when C*R>N.
 5. The apparatus of claim 1 wherein saidapparatus comprises P memory locations identified by addresses 0 throughP−1, wherein P is a positive integer greater than 1; and wherein saiddata switch is non-blocking for all combinations of addresses p+(c−1)for all p and all c, wherein 0≦p+(c−1)<P, wherein p is a positiveinteger and pε{0, . . . , P−1}, wherein c is a positive integer andcε{1, . . . C}, and wherein C is a positive integer and C≦N; whereinsaid data switch is blocking for at least one combination of addressesp+(c−1) for all p and all c when C>N; wherein said data switch isnon-blocking for all combinations of addresses p+N(r−1) for all p andall r, wherein 0≦p+N(r−1)<P, wherein r is a positive integer and rε{1, .. . R}, and wherein R is a positive integer and R≦N; and wherein saiddata switch is blocking for at least one combination of addressesp+N(r−1) for all p and all r when R>N.
 6. The apparatus of claim 5wherein said data switch is non-blocking for addresses p+(c−1)+N(r−1)for all p, all c, and all r, wherein 0≦p+(c−1)+N(r−1)<P, and wherein1≦C*R≦N.
 7. The apparatus of claim 1 wherein said apparatus comprises Pmemory locations identified by addresses 0 through P−1, wherein P is apositive integer greater than 1; and wherein said data switch isnon-blocking for all combinations of addresses p+(c−1)+N(r−1) for all p,all c, and all r, wherein 0≦p+(c−1)+N(r−1)<P, wherein p is a positiveinteger and pε{0, . . . , P−1}, wherein c is a positive integer andcε{1, . . . , C}, wherein r is a positive integer and rε{1, . . . , R},and wherein C and R are positive integers and 1≦C*R≦N; and wherein saiddata switch is blocking for at least one combination of addressesp+(c−1)+N(r−1) for all p and all c when C*R>N.
 8. An apparatuscomprising: (a) a processor comprising an N-word register, wherein N isa positive integer greater than one; (b) an N-port memory comprising Pmemory locations identified by addresses 0 through P−1, wherein P is apositive integer greater than one; (c) an N by N data switch interposedbetween said memory and said register that is: (i) non-blocking for allcombinations of addresses p+(c−1) for all p and all c, wherein0≦p+(c−1)<P, wherein p is a positive integer and pε{0, . . . , P−1},wherein c is a positive integer and cε{1, . . . , C}, and wherein C is apositive integer and C≦N; (ii) blocking for at least one combination ofaddresses p+(c−1) for all p and all c when C>N; (iii) non-blocking forall combinations of addresses p+N(r−1) for all p and all r, wherein0≦p+N(r−1)<P, wherein r is a positive integer and rε{1, . . . , R}, andwherein R is a positive integer and R≦N; and (iv) blocking for at leastone combination of addresses p+N(r−1) for all p and all r when R>N. 9.The apparatus of claim 8 wherein said data switch is (v) non-blockingfor addresses p+(c−1)+N(r−1) for all p, all c, and all r, wherein0≦p+(c−1)+N(r−1)<P, and wherein 1≦C*R≦N.
 10. The apparatus of claim 9wherein said data switch is (vi) blocking for at least one combinationof addresses p+(c−1)+N(r−1) for all p, all c, and all r, when C*R>N. 11.An apparatus comprising: (a) a processor comprising an N-word register,wherein N is a positive integer greater than one; (b) an N-port memorycomprising P memory locations identified by addresses 0 through P−1,wherein P is a positive integer greater than one; (c) an N by N dataswitch interposed between said memory and said register that is: (i)non-blocking for addresses p+(c−1)+N(r−1) for all p, all c, and all r,wherein 0≦p+(c−1)+N(r−1)<P, wherein p is a positive integer and pε{0, .. . , P−1}, wherein c is a positive integer and cε{1, . . . , C},wherein r is a positive integer and rε{1, . . . , R}, and wherein C andR are positive integers and 1≦C*R≦N; and (ii) blocking for at least onecombination of addresses p+(c−1)+N(r−1) for all p, all c, and all r,when C*R>N.